To increase memory density, memory products are conventionally formed as an array structure consisting of a number of single memory cells sharing the same word line (“WL”) and/or the same bit line (“BL”). FIG. 1 depicts a block diagram of an example nonvolatile memory array configured with a plurality of WL pads and BL pads in a direct probing characterization vehicle used for testing purposes according to the prior art. Prior art memory array 100 may be a nonvolatile memory array. In the diagram, prior art memory array 100 is shown comprising a plurality of WLs 102 and a plurality of BLs 104 arranged in a cross-point configuration, wherein each memory cell 106 is located at one of the intersections of the WLs 102 and BLs 104, with a corresponding set of WL pads 103 and BL pads 105 disposed around the periphery of the memory array 100. The WL pads 103 and/or BL pads 105 can be used for receiving a test probe device that can perform testing on the memory cells of the memory array according to one or more testing algorithms as would be appreciated by persons of ordinary skill in the art. In the diagram, the WLs 102 and BLs 104 are directly connected to the probing pads 103 and 105, respectively. Memory array 100 further includes a set of select transistors 107 that are used to gate signals driven out onto the BLs 104 of the array.
To access a specific memory cell, voltage bias levels are applied to the memory cell during an appropriate time period. When this happens, neighboring memory cells that share either the same WL and/or BL are known to suffer unwanted stress conditions. This can disturb the neighboring cells, and in some cases cause the value stored in the memory cell to change to an incorrect value (e.g., the stored bit value in the memory cell can be flipped from a zero to a one or from a one to a zero. Disturbance is the term of art used to describe such unwanted stress conditions from the array structure during operations such as writing data to the memory cells (Program), erasing data (Erase) stored in the memory cells, or reading data (Read) from the memory cells.
Nonvolatile memories such as for example floating gate memories, use high impedance conditions (“Hi-Z”) across the memory cell transistors of the neighboring memory cells to improve immunity to such disturbance. In floating gate memories, Program operations inject electrons from the memory cell transistor bulk or channel into the charge trap layer (floating gate), whereas Erase operations pull electrons out of the charge trap layer back into the bulk (or channel) of the memory cell transistor. The difference between the erased memory cells and erase-inhibited neighboring memory cells is the gate potential of the memory cell transistor.
For example, Flash memory uses a high gate-to-channel (or well or bulk) electric field across the cell transistor of the memory cell to Erase a memory cell or block of cells. After a Program operation the selected memory cells or block of cells should be erased and neighboring memory cells should not be erased. The electric potential gap between the gate and bulk or channel of the cell transistor should be high for the erased memory cells and should be held close to zero volts for the erase-inhibited neighboring memory cells. Therefore, in prior art solutions the operating conditions of the memory cells should be carefully selected to avoid inducing a high electric field in the neighboring memory cells that are not being accessed, but that share either the same WL or BL. This can help prevent the bit values (zero or one) programmed into the neighboring memory cells from being adversely affected during any Program, Erase and/or Read operations.
In general, floating gate nonvolatile memories use Hi-Z conditions for the neighboring memory cells to counteract the electric field disturbance that may arise across the neighboring memory cell as a result of accessing the target memory cells. To cancel out the electric field across the gate and channel of the neighboring memory cell transistors, prior art solutions apply a reversed bias having the same magnitude between the gate voltage and the channel (or well or bulk) voltage during a specified time period to inhibit erasing the neighboring memory cells. In prior art solutions, this is accomplished using sophisticated circuit design techniques which require additional circuits and precise synchronization.
Such circuit techniques are employed in conventional methods to prevent the gate potential of the erase-inhibited neighboring memory cells from dropping too low. If the gate potential of the erase-inhibited memory cells drops too low, the reverse bias applied across the neighboring memory cells may not be high enough to inhibit it from flipping to an incorrect value, causing a failure in the memory array. The root cause of such failure stems from the characteristics of the transistors that drive Program, Erase or Read signals out onto the nonvolatile memory cells of the memory array. The gate potential of the neighboring memory cells can become too low due to high leakage current from the transistors that drive signals out to the memory cells and/or high parasitic capacitance coming from the driving transistors. If the drain (or source) of driving transistors are leaky or the gate capacitance and/or junction capacitance of the driving transistors is high, the memory cell gate potential becomes too low and the memory cells are accordingly susceptible to being inadvertently erased.
Additionally, during testing of the memory array, the gate capacitance and/or junction capacitance of the memory cell transistors can become too low because of the high parasitic loading capacitance stemming from the testing device (e.g., test probe) structure, routing, and/or pad probing.